Altera Corporation (NASDAQ: ALTR) is the pioneer of programmable logic solutions, enabling system and semiconductor companies to rapidly and cost effectively innovate, differentiate, and win in their markets. Altera offers FPGAs, CPLDs, and ASICs in combination with software tools, intellectual property, and customer support to provide high-value programmable solutions to over 13,000 customers worldwide. Altera was founded in 1983 and had annual revenues in 2010 of US$1.95 billion. Altera is headquartered in San Jose, California, and employs approximately 2,600 people in 19 countries.
Altera is a dynamic, growing company with an overall commitment to excellence. We expect continuing improvement in everything we do. We want to lead, not follow—in our products, technology, service, and employee relations. We strive to be the best.
Part of Altera's overall philosophy of excellence is a commitment to the development and well being of our employees. Only with the best people performing excellent work can Altera continue our industry leadership. We believe each person is important and we will attempt to give every employee opportunities to succeed and grow.
Come discover and create your future in Altera.
Section Head, Design Engineering (Protocol IP) Work locations Penang - Bayan Lepas
Closing Date:17-9-11
Responsibilities:
* Manage a group of 5-6 engineers.
* Project management: resource planning, project scheduling and tracking, task risk assessment, provide development updates to management team.
* Main interface for IP Development team to cross functional teams (IC Engineering, Hardcopy Design Center, Product Engineering, Technical Services) and matrix managers.
* Drive project deliverables to completion, gate-keeper to code quality, identify process improvement, drive automation and align to department goals & objectives.
* Define project roadmap with matrix managers, translate goals into project plan and execute it.
* Build the team competency to intercept new IP development techniques and grooming technical experts.
* Career development, carry out team competency gap analysis, establish personal development plan to align with teams’ objective with success indicators.
Requirements:
* Bachelors or post-graduate degree in EE, CE or CS, or equivalent, with a minimum of 7 years of relevant experience.
* Strong skills in communication, initiative, promote innovation and teamwork.
* Highly motivated to learn and adapt to fast-changing technologies and environments.
* Familiarity with Verilog and/or VHDL is required.
* Familiarity or experience with RTL verification is a strong plus.
* Familiarity with Perl, C++, Java and shell scripts is a plus.
* Knowledge of high speed serial system interfaces (such as Ethernet, PCI Express, CPRI or Serial Rapid IO) is an added advantage.
Design Engineer (Embedded Processor), Senior/Staff Work locations Penang
Closing Date:17-9-11
Responsibilities:
* Architecture and implementation of new additions to our Embedded Processor & Peripheral IP portfolio.
* Characterizing system performance and optimizing our solutions to target applications.
* Verification (e.g. verification IP/methodologies/framework, bus functional models, regression tests).
* Device support and features.
* Together with the team, carrying a complete processor architecture through RTL design and verification to a complete, finished product.
* Your dynamic, innovative team will challenge and inspire you, and in return you will bring fresh ideas and years of experience to our constant effort of improving our technologies, processes, and development practices.
Requirements:
* Bachelors or postgraduate degree in Electronics Engineering, Computer Engineering or Computer Science, or equivalent, with a minimum of 3 years of relevant experience including experience with FPGA/ASIC design flows.
* Familiarity or experience in RTL design with Verilog and/or VHDL is required.
* Familiarity or experience with RTL verification and timing analysis/closure on Linux/UNIX platforms is a strong plus.
* Strong knowledge in Processor and/or SoC Architecture is a strong plus.
* Familiarity with Perl, C++, Java and shell scripts is a plus.
* Strong skills in communication, initiative, promote innovation and teamwork.
* Highly motivated to learn and adapt to fast-changing technologies and environments.
* Demonstrates fundamental values such as accountability, integrity and a winning mindset.
Design Engineer, Entry/Advanced Work locations Penang
Closing Date:17-9-11
Responsibilities:
To collaborate with global engineering and technical marketing teams in defining, developing and productizing Altera’s IP solution and design tools suite. Project responsibilities shall cover one or more of the areas listed below.
• Embedded systems (e.g. softcore processor, sub-system cores)
• High-speed serial interface IP with transceivers (e.g. Ethernet, 1588, CPRI)
• Memory IP (e.g. DDR2/3, QDRII/II+, RLDRAMII/III)
• Broadcast IP (e.g. DisplayPort, SDI)
• System Builder Tools (for embedded systems and DSP systems)
• DSP IP ( e.g. CIC, FIR, Reed Soloman, Viterbi, NCO)
• Video IP (e.g. Scaler, Deinterlacer, Mixer, Filters)
• Verification IP (e.g. verification IP/methodologies/framework bus functional models)
• New product release or rollout support
• Customer technical support
• Device support and features
Requirements:
• Bachelors, Masters or PhD in Computer Engineering / Electronics Engineering with minimum 1 year of relevant experience. Recent college graduates with CGPA > 3.2 are encouraged to apply.
• Highly competent in Verilog/VHDL and logic design.
• Hands-on experience in RTL design, simulation, verification and timing analysis/closure on Linux/UNIX platforms.
• Competent in scripting (TCL/Shell/Perl).
• Knowledge in C/C++/Java will be an added advantage.
• Knowledge of algorithms and methodologies in the relevant IP areas.
• Experience with FPGA products and solutions is preferred.
• Strong skills in communication, resourcefulness, initiative, innovation and teamwork.
• Highly motivated to learn and adapt to fast-changing technologies and environments.
• Demonstrates fundamental values such as accountability, integrity and a winning mindset.
Design Engineer (Memory Interface), Senior/Staff Work locations Penang
Closing Date:17-9-11
Responsibilities:
* You will be part of an engineering team focusing on designing External Memory Interfaces IP.
* You will be working on advanced device architectures, design definition, implementation and verification.
* Defining IP specification in collaboration with global engineering and marketing teams.
* Designing Memory IP (e.g. DDR2, DDR3, QDRII/+, and RLDRAM II).
* Defining test plan and developing testbench for functional verification.
* New product release or rollout support.
* Customer technical support.
* Device support and features.
Requirements:
* Bachelors, Masters or PhD in Computer Engineering or Electronics Engineering.
* Minimum 5 years of relevant experience.
* Highly competent in Verilog/VHDL and logic design.
* Hands-on experience in RTL design, simulation, verification and timing analysis/closure on Linux/
* UNIX platforms.
* Competent in scripting (TCL/Shell/Perl).
* Knowledge in the External Memory Interface ( e.g. DDR2, DDR3, QDRII/+, and RLDRAM II) is a
* strong plus.
* Knowledge in OVM, VMM or UVM verification methodology is a plus.
* Strong skills in communication, resourcefulness, initiative, innovation and teamwork.
* Highly motivated to learn and adapt to fast-changing technologies and environments.
* Demonstrates fundamental values such as accountability, integrity and a winning mindset.
Design Engineer (Communications Protocols), Senior / Staff Work locations Penang
Closing Date:17-9-11
Responsibilities:
* High-speed serial interface IP with transceivers (e.g., Ethernet, 1588, CPRI, RapidIO, SDI).
* Architecture and design (based on latest specifications, RTL design).
* Verification (e.g., verification IP/methodologies/framework, bus functional models, regression tests).
* New product release or rollout support.
* Customer technical support.
* Device support and features.
Requirements:
* Bachelors or Masters degree in Electronics Engineering, Computer Engineering, Computer Science, or its equivalent.
* Minimum 5 years of relevant experience.
* Familiarity or experience in RTL design with Verilog and/or VHDL is required.
* Familiarity or experience with RTL verification and timing analysis/closure on Linux/UNIX platforms is a strong plus.
* Knowledge of high speed serial system interfaces (such as Ethernet, IEEE 1588, CPRI or Serial Rapid IO) is a strong plus.
* Familiarity with Perl, C++, Java and shell scripts is a plus.
* A team player with strong communication skills, is innovative, and has initiative.
* Highly motivated to learn and adapt to fast-changing technologies and environments.
* Demonstrates fundamental values such as accountability, integrity and a winning mindset.
Software Engineer (Software QA), Advanced/Senior Work locations Penang
Closing Date:17-9-11
Responsibilities:
* As a Software QA Engineer, you will work with a local team of Software QA engineers and our counterparts in North America and Canada technology centre.
* You are responsible to execute and monitor the batch run on Altera Complete Design Suite (ACDS) regression tests on Altera Resource Computing farm (ARC). You will need to analyze test run results and troubleshoot upcoming test infrastructure issues. You are expected to continuously seek opportunity to optimize ARC resource usage in ACDS regression test runs.
* You will have the opportunity to learn about ACDS products and work with other Software QA engineers to perform testing on these ACDS products.
* You will need to understand the test requirements, explore different ways for test automation and deliver well-coded automated testing solutions that complement manual test efforts.
* You will need to explore and research different ways to improve test effectiveness, drive towards best practices (e.g. test driven development, agile development, scrum methodology etc) that help to improve quality of ACDS products.
* You will involve in developing quality management system for the department.
Requirements:
* Bachelors or Master degree in Computer Science, Computer Engineering, Electronic Engineering or equivalent with a minimum of 3 - 4 years experience in the relevant field.
* The required skills are, but not limited to, scripting programming (e.g. perl, tcl, python), web programming (e.g. PHP, dJango, Javascript) and database management.
* Knowledge in Quality Management System is an added advantage.
* Possess excellent communications and interpersonal skills and a team player.
* Ability to work in a fast-paced, collaborative, and often intense project environment.
* Self driven and requirement minimal supervision in driving projects.
Software Engineer (Performance Analysis), Advanced/Senior Work locations Penang
Closing Date:17-9-11
Responsibilities:
* Work with a local team of engineers and experts in our Toronto, Canada research facility to assemble a set of large, complex designs used to optimize our software.
* Create strategies to measure quality of features in the Altera Complete Design Suite.
* Create automation tools for the conversion and quality measurement of large designs.
* Create verification tools for Quartus II and IP cores. Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design’s reaction to different stimuli, and configure the target device with the programmer.
Requirements:
* Bachelors or Masters degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science or equivalent with minimum 4 years of relevant experience.
* Expertise in scripting languages (Tcl/Perl/Python) and C/C++.
* Expertise in VHDL/Verilog and strong design verification experience are strong assets.
* Highly exceptional engineers with less experience will also be considered.
* Knowledge in RTL or EDA industry applications or Altera Products is preferred.
* Ability to work in a fast-paced, collaborative, and often intense project environment.
* Excellent communication and interpersonal skills, and a team-player.
Software Engineer (Device Configuration), Advanced/Senior Work locations Penang
Closing Date:17-9-11
Responsibilities:
* Responsible for driving and developing Quartus II Parallel Flash Loader (PFL) and Serial Flash Loader (SFL) Megafunction. Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design’s reaction to different stimuli, and configure the target device with the programmer.
* You will be also working closely with the Marketing Department to support various customer requests.
Requirements:
* Bachelors or Masters degree in Computer Science, Computer Engineering, Electronic Engineering, or its equivalent.
* Minimum of 3 - 4 years experience in the relevant field.
* Smart, motivated, interested in working on both hardware and software designs.
* Strong in C/C++ programming language.
* Experience in RTL (Verilog & VHDL) and Digital Circuit Design is preferred.
* Knowledge about EDA tools (e.g. Simulation, Verification), FPGA development, and CAD tool algorithms will be a plus.
* A team player with excellent communication and interpersonal skills.
* Ability to work in a fast-paced, collaborative, and often intense project environment.
* Self driven and requires minimal supervision in driving projects.
Software Engineer (Core Features), Advanced/Senior Work locations Penang
Closing Date:17-9-11
Responsibilities:
* As a Core Features Software Engineer, you will be working closely with R&D department in developing a solution to prototype customer designs with Stratix® series FPGAs, and then migrate the designs seamlessly to HardCopy series ASICs for volume production. Altera's HardCopy® series ASICs enable customer to take their system designs from prototyping into volume production much faster and with much less risk.
* You will also need to have strong interest in working with various teams and perform support and helping to debug customer designs.
Requirements:
* Bachelors or Masters degree in Computer Science, Computer Engineering, Electronic Engineering or equivalent with a minimum of 3 years experience in the relevant field.
* Smart, motivated, interested on working both hardware and software.
* Strong in C/C++ programming language.
* Experience in RTL (Verilog & VHDL), Digital Circuit Design and TCL is preferred.
* Knowledge about EDA tools (e.g. Simulation, Verification), FPGA development and CAD tool algorithm will be a plus.
* Possess excellent communications and interpersonal skills and a team player.
* Ability to work in a fast-paced, collaborative, and often intense project environment.
* Self driven and requirement minimal supervision in driving projects.
Only shortlisted candidates will be notified.
Apply Online
Altera Corporation (M) Sdn Bhd
Plot 6, Bayan Lepas Technoplex Medan Bayan Lepas,
Bayan Lepas 11900.
Website: http://www.altera.com/
19.57
